SH7032 Datasheet, PDF (312/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
TCNT value
GRB
H' 0250
H' 0200
H' 0100
H' 0000
BRA
GRA
H' 0200
H' 0250
TIOCB
TIOCA
Counter cleared by compare match B
H' 0100
H' 0200
H' 0100
H' 0200
H' 0200
Time
Toggle
output
Toggle
output
Compare match A
Figure 10.48 Buffer Mode Operation Example 1 (Output Compare Register)
CK
TCNT
n
n+1
Compare
match signal
Buffer
transfer signal
BR
N
GR
n
N
Figure 10.49 Compare Match Timing Example for Buffer Operation
Figure 10.50 shows an example of input capture operation in buffer mode between GRA and BRA
with GRA as an input capture register. TCNT is cleared by input capture B. The falling edge is
selected as the input capture edge at TIOCB. Both edges are selected as input capture edges at
TIOCA. When the TCNT value is stored in GRA by input capture A, the previous GRA value is
transferred to BRA. The timing is shown in figure 10.51.
Rev. 7.00 Jan 31, 2006 page 286 of 658
REJ09B0272-0700