SH7032 Datasheet, PDF (668/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
A.2.66 Next Data Enable Register A (NDERA)
TPC
Start Address: H'5FFFFF3
Bus Width: 8/16
Bit
Initial value
Read/Write
7
NDER7
0
R/W
6
NDER6
0
R/W
5
NDER5
0
R/W
4
NDER4
0
R/W
3
NDER3
0
R/W
2
NDER2
0
R/W
1
NDER1
0
R/W
0
NDER0
0
R/W
Table A.67 NDERA Bit Functions
Bit Bit Name
7–0 Next data enable 7–0
(NDER7–NDER0)
Value
0
1
Description
Disable TPC output TP7–TP0 disabled (Initial value)
(Transfer from NDR7–NDR0 to PB7–PB0 disabled)
TPC output TP7–TP0 enabled
(Transfer from NDR7–NDR0 to PB7–PB0 enabled)
A.2.67 Next Data Enable Register B (NDERB)
TPC
Start Address: H'5FFFFF2
Bus Width: 8/16
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
NDER8
0
R/W
Table A.68 NDERB Bit Functions
Bit Bit Name
Value Description
7–0 Next data enable 7–0 0
(NDER15–NDER8)
TPC output TP15–TP8 disabled
(Initial value)
(Transfer from NDR15–NDR8 to PB15–PB8 disabled)
1
TPC output TP15–TP8 enabled
(Transfer from NDR15–NDR8 to PB15–PB8 enabled)
Rev. 7.00 Jan 31, 2006 page 642 of 658
REJ09B0272-0700