SH7032 Datasheet, PDF (205/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 9 Direct Memory Access Controller (DMAC)
Section 9 Direct Memory Access Controller (DMAC)
9.1 Overview
The SuperH microcomputer chip includes a four-channel direct memory access controller
(DMAC). The DMAC can be used in place of the CPU to perform high speed transfers between
external devices that have DACK (transfer request acknowledge signal), external memory,
memory-mapped external devices, on-chip memory, and on-chip supporting modules (excluding
the DMAC itself). Using the DMAC reduces the burden on the CPU and increases overall
operating efficiency.
9.1.1 Features
The DMAC has the following features.
• Four channels
• Four Gbytes of address space in the architecture
• Byte or word selectable as data transfer unit
• 65536 transfers (maximum)
• Single address mode transfers (channels 0 and 1): Either the transfer source or transfer
destination (peripheral device) is accessed by a DACK signal (selectable) while the other is
accessed by address. One transfer unit of data is transferred in each bus cycle.
Device combinations for which transfer is possible:
 External device with DACK and memory-mapped external device (including external
memories)
 External device with DACK and memory-mapped external memory
• Dual address mode transfer (channels 0–3): Both the transfer source and transfer destination
are accessed by address. One transfer unit of data is transferred in 2 bus cycles.
Device combinations for which transfer is possible:
 Two external memories
 External memory and memory-mapped external device
 Two memory-mapped devices
 External memory and on-chip memory
 Memory-mapped external device and on-chip supporting module (excluding the DMAC)
 External memory and on-chip memory
 Memory-mapped external device and on-chip supporting module (excluding the DMAC)
 Two on-chip memories
Rev. 7.00 Jan 31, 2006 page 179 of 658
REJ09B0272-0700