SH7032 Datasheet, PDF (283/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
Buffer Mode:
• When GR is an output compare register: The BR value of each channel is transferred to GR
when a compare match occurs.
• When GR is an input capture register: The TCNT value is transferred to GR when an input
capture occurs and simultaneously the value previously stored in GR is transferred to BR.
• Complementary PWM mode: When TCNT3 and TCNT4 change count directions, the BR
value is transferred to GR.
• Reset-synchronized PWM mode: The BR value is transferred to GR upon a GRA3 compare
match.
10.4.2 Basic Functions
Counter Operation: When a start bit (STR0–STR4) in the timer start register (TSTR) is set to 1,
the corresponding timer counter (TCNT) starts counting. There are two counting modes: a free-
running mode and a periodic mode.
• Procedure for selecting counting mode (figure 10.14):
1. Set bits TPSC2–TPSC0 in TCR to select the counter clock source. If an external clock
source is selected, set bits CKEG1 and CKEG0 in TCR to select the desired edge of the
external clock signal.
2. To operate as a periodic counter, set CCLR1 and CCLR0 in TCR to select whether to clear
TCNT at GRA compare match or GRB compare match.
3. Set GRA or GRB selected in step 2 as an output compare register using the timer I/O
control register (TIOR).
4. Write the desired cycle value in GRA or GRB selected in step 1.
5. Set the STR bit in TSTR to 1 to start counting.
Rev. 7.00 Jan 31, 2006 page 257 of 658
REJ09B0272-0700