SH7032 Datasheet, PDF (510/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 20 Electrical Characteristics
Item
Symbol Min Max
Unit Figures
AH delay time 1
t_AHD1
AH delay time 2
t_AHD2
Multiplexed address delay time t_MAD
Multiplexed address hold time t_MAH
DACK0, DACK1 delay time 1 t_DACD1
— 20
— 20
— 30
0
—
— 23
ns 20.19
ns
ns
ns
ns 20.8, 20.9, 20.11–
20.14, 20.19, 20.20
DACK0, DACK1 delay time 2 t_DACD2
DACK0, DACK1 delay time 3*⁷ t_DACD3
— 23
— 20
ns
ns 20.9, 20.13, 20.14,
20.19
DACK0, DACK1 delay time 4 t_DACD4
— 20
ns 20.11, 20.12
DACK0, DACK1 delay time 5 t_DACD5
Read delay time 35% duty*² t_RDD
50% duty
Data setup time for CAS
t_DS
— 20
ns
— t_cyc × 0.35 + 12 ns 20.8, 20.9, 20.11–
—
t_cyc × 0.5 + 15 ns ^{20.15, 20.19}
0*⁵ —
ns 20.11, 20.13
CAS setup time for RAS
t_CSR
10 —
ns 20.16–20.18
Row address hold time
t_RAH
10 —
ns 20.11, 20.13
Write command hold time
t_WCH
Write command
setup time
35% duty*² t_WCS
50% duty t_WCS
15 —
0
—
0
—
ns
ns 20.11
ns
Access time from
CAS precharge*⁶
t_ACP
t_cyc —
−20
ns 20.12
Notes: 1. HBS and LBS signals are 25 ns.
2. When frequency is 10 MHz or more.
3. n is the number of wait cycles.
4. Access time from addresses A0 to A21 is tcyc-25 ns.
5. –5ns for parity output of DRAM long-pitch access.
6. It is not necessary to meet the t_RDS specification as long as the access time
specification is met.
7. In the relationship of t_CASD2 and t_CASD3 with respect to t_DACD3, a Min-Max combination
does not occur because of the logic structure.
Rev. 7.00 Jan 31, 2006 page 484 of 658
REJ09B0272-0700