SH7032 Datasheet, PDF (54/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 2 CPU
Table 2.9 Instruction Formats
Instruction Format
0 format
15
xxxx xxxx xxxx
0
xxxx
n format
15
xxxx nnnn
0
xxxx xxxx
m format
15
xxxx mmmm xxxx
0
xxxx
Source Operand
—
Destination
Operand
—
Example
NOP
—
nnnn: Register MOVT Rn
direct
Control register or
system register
Control register or
system register
mmmm: Register
direct
nnnn: Register
direct
STS MACH,Rn
nnnn: Register
indirect with
pre-decrement
STC.L SR,@-Rn
Control register or LDC
system register
Rm,SR
mmmm: Register
indirect with
post-increment
mmmm: Register
indirect
mmmm: PC relative
using Rm
Control register or LDC.L @Rm+,SR
system register
—
JMP @Rm
—
BRAF Rm
Rev. 7.00 Jan 31, 2006 page 28 of 658
REJ09B0272-0700