SH7032 Datasheet, PDF (324/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
10.6.5 Contention between TCNT Write and Overflow/Underflow
If an overflow occurs in the T3 state of a TCNT write cycle, writing takes priority over counter
incrementing. OVF is set to 1. The same applies to underflows. The timing is shown in figure
10.62.
TCNT write cycle
T1
T2
T3
CK
Address
Internal
write signal
TCNT
input clock
Overflow
signal
TCNT address
TCNT
OVF
H'FFFF
M
TCNT write data
Figure 10.62 Contention between TCNT Write and Overflow
Rev. 7.00 Jan 31, 2006 page 298 of 658
REJ09B0272-0700