SH7032 Datasheet, PDF (91/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

4.8 Notes
Section 4 Exception Handling
4.8.1 Value of the Stack Pointer (SP)
An address error occurs if the stack is accessed for exception handling when the value of the stack
pointer (SP) is not a multiple of four. Therefore, a multiple of four should always be stored in the
SP.
4.8.2 Value of the Vector Base Register (VBR)
An address error occurs if the vector table is accessed for exception handling when the value of
the vector base register (VBR) is not a multiple of four. Therefore, VBR should always be set to a
multiple of four.
4.8.3 Address Errors Caused by Stacking During Address Error Exception Handling
If the stack pointer is not a multiple of four, address errors will occur in the exception handling
(interrupt, etc.) stacking. After the exception handling ends, the CPU will then shift to address
error exception handling. An address error will also occur during the address error exception
handling stacking, but the CPU is set up to ignore the address error so that it can avoid an infinite
series of address errors. This allows it to shift program control to the address error exception
handling routine and handle the error.
When an address error does occur in exception handling stacking, the stacking bus cycle (write) is
executed. In SR and PC stacking, four is subtracted from each of the SPs so the SP values are not
multiples of four after stacking either. Since the address value output during stacking is the SP
value, the address that produced the error is exactly what is output. In such cases, the stacked write
data will be undefined.
Rev. 7.00 Jan 31, 2006 page 65 of 658
REJ09B0272-0700