SH7032 Datasheet, PDF (149/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Bus State Controller (BSC)
To prevent RTCSR from being written incorrectly, it must be written by a different method from
most other registers. A word transfer operation is used, H'69 is written in the upper byte, and the
actual data is written in the lower byte. For details, see section 8.2.11, Notes on Register Access.
Bit
Initial value
Read/Write
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
8.2.9 Refresh Time Constant Register (RTCOR)
The refresh time constant register (RTCOR) is a 16-bit read/write register that sets the compare
match cycle used with RTCNT. The values in RTCOR and RTCNT are constantly compared.
When they match, the compare match flag (CMF) is set in RTCNT and RTCSR is cleared to
H'0000. If the RFSHE bit in RCR is set to 1 when this happens, a CAS-before-RAS (CBR) refresh
is performed. When the CMIE bit in RTCSR is also set to 1, a compare match interrupt (CMI) is
generated.
Bits 15–8 are reserved and cannot be used to set the cycle. These bits are always read as 0.
RTCOR is initialized to H'00FF by a power-on reset, but is not initialized by a manual reset or in
standby mode.
To prevent RTCOR from being written incorrectly, it must be written by a different method from
most other registers. A word transfer operation is used, H'96 is written in the upper byte, and the
actual data is written in the lower byte. For details, see section 8.2.11, Notes on Register Access.
Bit
Initial value
Read/Write
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
Rev. 7.00 Jan 31, 2006 page 123 of 658
REJ09B0272-0700