SH7032 Datasheet, PDF (493/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 19 Power-Down State
Bits 5–0Reserved: Bit 5 is a read-only bit that is always read as 0. Only write 0 in bit 5.
Writing to bits 4–0 is disabled. These bits are always read as 1.
19.3 Sleep Mode
19.3.1 Transition to Sleep Mode
Execution of the SLEEP instruction when the standby bit (SBY) in the standby control register
(SBYCR) is cleared to 0 causes a transition from the program execution state to sleep mode.
Although the CPU halts immediately after executing the SLEEP instruction, the contents of its
internal registers remain unchanged. The on-chip supporting modules do not halt in sleep mode.
19.3.2 Exiting Sleep Mode
Sleep mode is exited by an interrupt, DMA address error, power-on reset, or manual reset.
Exit by Interrupt: When an interrupt occurs, sleep mode is exited and interrupt exception
handling is executed. Sleep mode is not exited if the interrupt cannot be accepted because its
priority level is equal to or less than the mask level set in the CPU’s status register (SR). Likewise,
sleep mode is not exited if the interrupt is disabled by the on-chip supporting module.
Exit by DMA Address Error: If the DMAC operates during sleep mode and a DMA address
error occurs, sleep mode is exited and DMA address error exception handling is executed.
Exit by Power-On Reset: If the RES signal goes low while the NMI signal is high, sleep mode is
exited and the power-on reset state is entered. If the NMI signal is brought from low to high in
order to set the chip for a power-on reset, an NMI interrupt will occur whenever the rising edge of
NMI is selected as the valid edge (with NMI edge select bit NMIE in the interrupt control register
(ICR) of the interrupt controller). When this occurs, the NMI interrupt clears sleep mode.
Exit by Manual Reset: If the RES signal goes low while the NMI signal is low, sleep mode is
exited and the manual reset state is entered. If the NMI signal is brought from high to low in order
to set the chip for a manual reset, sleep mode will be exited by an NMI interrupt whenever the
falling edge of NMI is selected as the valid edge (with the NMIE bit).
Rev. 7.00 Jan 31, 2006 page 467 of 658
REJ09B0272-0700