SH7032 Datasheet, PDF (184/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Bus State Controller (BSC)
• RAS up mode: When the RASD bit is cleared to 0, the RAS signal reverts to high whenever a
DRAM access pauses for access to another space. Burst operation continues only while
DRAM access is continuous. Figure 8.28 shows the timing when an external memory space
access occurs during burst operation in RAS up mode.
CK
A21–
A0
RAS
DRAM access
External memory
space access _{DRAM access}
T_p
T_r
T_c
T_c
T1
T_p
T_r
T_c
Column Column External memory
address 1 address 2
address
Column
address 3
Row address
Row address
CAS
AD15–
AD0
Data 1 Data 2
External
memory data
Figure 8.28 RAS Up Mode
Data 3
8.5.6 Refresh Control
The BSC has a function for controlling DRAM refreshing. By setting the refresh mode bit
(RMODE) in the refresh control register (RCR), either CAS-before-RAS refresh (CBR) or self-
refresh can be selected. When no refresh is performed, the refresh timer counter (RTCNT) can be
used as an 8-bit interval timer.
CAS-Before-RAS Refresh (CBR): A refresh is performed at an interval determined by the input
clock selected with clock select bits 2–0 (CKS2–CKS0) in the refresh timer control/status register
(RTCSR) and the value set in the refresh time constant register (RTCOR). Set the values of
RTCOR and CKS2–CKS0 so they satisfy the refresh interval specifications of the DRAM being
used.
To perform a CBR refresh, clear the RMODE bit in RCR to 0 and then set the refresh control bit
(RFSHE) bit to 1. Also write the required values to RTCNT and RTCOR. When the clock is
subsequently selected with the CKS2–CKS0 bits in RTCSR, RTCNT will begin to increment from
its current value. The RTCNT value is constantly compared with the RTCOR value and a CBR
Rev. 7.00 Jan 31, 2006 page 158 of 658
REJ09B0272-0700