SH7032 Datasheet, PDF (279/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10.3 CPU Interface
Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
10.3.1 16-Bit Accessible Registers
The timer counters (TCNT), general registers A and B (GRA, GRB), and buffer registers A and B
(BRA, BRB) are 16-bit registers. The SH CPU can access these registers a word at a time using a
16-bit data bus. Byte access is also possible. Read and write operations performed on TCNT in
word units are shown in figures 10.6 and 10.7. Byte-unit read and write operations on TCNTH and
TCNTL are shown in figures 10.8 to 10.11.
Internal data bus
H
CPU _L
Bus
interface
H
Module
L
data bus
TCNTH
TCNTL
Figure 10.6 TCNT Access (CPU to TCNT (Word))
Internal data bus
H
CPU _L
Bus
interface
H
Module
L
data bus
TCNTH
TCNTL
Figure 10.7 TCNT Access (TCNT to CPU (Word))
Internal data bus
H
CPU _L
Bus
interface
H
Module
L
data bus
TCNTH
TCNTL
Figure 10.8 TCNT Access (CPU to TCNT (Upper Byte))
Rev. 7.00 Jan 31, 2006 page 253 of 658
REJ09B0272-0700