SH7032 Datasheet, PDF (622/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
Table A.28 CHCR0–CHCR3 Bit Functions
Bit Bit name
Value
Description
15,14 Destination address 0 0
mode bits 1, 0 (DM1,
DM0)
01
Destination address is fixed
(Initial value)
Destination address incremented (+1 for byte transfer;
+2 for word transfer)
10
Destination address decremented (–1 for byte
transfer; –2 for word transfer)
11
Reserved (cannot be set)
13,12 Source address mode 0 0
bits 1, 0 (SM1, SM0) _{0 1}
Source address is fixed
(Initial value)
Source address incremented (+1 for byte transfer;
+2 for word transfer)
10
Source address decremented (–1 for byte transfer;
–2 for word transfer)
11–8 Resource select bits
3–0 (RS3–RS0)
11
Reserved (cannot be set)
0 0 0 0 DREQ (external request*¹)
(Dual address mode)
(Initial value)
0 0 0 1 Reserved (cannot be set)
0 0 1 0 DREQ (external request*¹) (Single address mode*²)
0 0 1 1 DREQ (external request*¹) (Single address mode*³)
0 1 0 0 RXIO (transfer request by receive-data-full interrupt of
on-chip SCI0)*⁴
0 1 0 1 TXIO (transfer request by transmit-data-empty
interrupt of on-chip SCI0)*⁴
0 1 1 0 RXI1 (transfer request by receive-data-full interrupt of
on-chip SCI1)*⁴
0 1 1 1 TXI1 (transfer request by transmit-data-empty
interrupt of on-chip SCI1)*⁴
1 0 0 0 IMIA0 (input capture A/compare match A interrupt
request of on-chip ITU0)*⁴
1 0 0 1 IMIA1 (input capture A/compare match A interrupt
request of on-chip ITU1)*⁴
1 0 1 0 IMIA2 (input capture A/compare match A interrupt
request of on-chip ITU2)*⁴
Rev. 7.00 Jan 31, 2006 page 596 of 658
REJ09B0272-0700