SH7032 Datasheet, PDF (602/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
Table A.9 ADCSR Bit Functions
Bit Bit name
Value Description
7 A/D end flag (ADF) 0
Clear conditions: (1) 0 written in ADF after reading ADF =
1; (2) DMAC started by ADI interrupt and A/D converter
register is accessed
(Initial value)
1
Set Conditions: (1) Single mode: A/D conversion ends;
(2) Scan mode: A/D conversion of all channels set has
ended
6 A/D interrupt enable 0
(ADF)
Interrupt requested by A/D conversion (ADI) disabled
(Initial value)
1
Interrupt requested by A/D conversion (ADI) enabled
5 A/D start (ADST)
0
Disable A/D conversion
(Initial value)
1
(1) Single mode: Start A/D conversion and when
conversion ends, automatically cleared to zero; (2) Scan
mode: Start A/D conversion and sequentially continue
converting the selected channels until cleared to 0 by
software, reset, or standby mode
4 Scan mode (SCAN) 0
Single mode
(Initial value)
1
Scan mode
3 Clock select (CKS) 0
Conversion time = 236 cycles (max)
(Initial value)
1
Conversion time = 134 cycles (max)
2–0 Channel select 2–0 CH2 CH1 CH0 Single mode
Scan mode
0
0 0 AN0 (Initial value) AN0 (Initial value)
1 AN1
AN0, AN1
1 0 AN2
AN0–AN2
1 AN3
AN0–AN3
1
0 0 AN4
AN4
1 AN5
AN4, AN5
1 0 AN6
AN4–AN6
1 AN7
AN4–AN7
Rev. 7.00 Jan 31, 2006 page 576 of 658
REJ09B0272-0700