SH7032 Datasheet, PDF (616/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
A.2.22 Buffer Registers B3, 4 (BRB3, BRB4)
Start Address: H'5FFFF2E (channel 3), H'5FFFF3E (channel 4)
Bus Width: 8/16/32
Bit
15
14
13
12
11
10
9
ITU
8
Initial value
Read/Write
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table A.23 BRB3, BRB4 Bit Functions
Bit
15–0
Bit name
Buffer registers used for output
compare/input capture
Description
Output compare register: Transfers to GRB the
value stored up to compare match generation
Input capture register: Stores the value stored in
GRB up to input capture signal generation
Rev. 7.00 Jan 31, 2006 page 590 of 658
REJ09B0272-0700