SH7032 Datasheet, PDF (276/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
Bit
7
6
5
4
Initial value
—
—
—
—
*¹
1
1
1
Read/Write
—
—
—
—
Notes: 1. Undefined
2. Only 0 can be written, to clear the flag.
3
2
1
0
—
OVF IMFB IMFA
1
0
0
0
— R/(W)*² R/(W)*² R/(W)*²
Bits 7–3—Reserved: Bit 7 is read as undefined. Bits 6–3 are always read as 1. The write value to
bit 7 should be 0 or 1. The write value to bits 6–3 should always be 1.
Bit 2—Overflow Flag (OVF): OVF indicates that a TCNT overflow/underflow has occurred.
Bit 2: OVF
Description
0
Clearing condition: Read OVF when OVF = 1, then write 0 in OVF (Initial value)
1
Setting condition: TCNT overflow from H'FFFF to H'0000 or underflow from
H'0000 to H'FFFF
Note:
A TCNT underflow occurs when the TCNT up/down-counter is functioning. It may occur in
the following cases: (1) When channel 2 is set to phase counting mode (MDF bit in TMDR is
1), or (2) when channel 3 and 4 are set to complementary PWM mode (CMD1 bit in TFCR
is 1 and CMD0 bit is 0).
Bit 1—Input Capture/Compare Match B (IMFB): IMFB indicates a GRB compare match or
input capture.
Bit 1: IMFB
0
1
Description
Clearing condition: Read IMFB when IMFB = 1, then write 0 in IMFB
(Initial value)
Setting conditions:
• GRB is functioning as an output compare register and TCNT = GRB
• GRB is functioning as an input capture register and the value of TCNT is
transferred to GRB by an input capture signal
Rev. 7.00 Jan 31, 2006 page 250 of 658
REJ09B0272-0700