SH7032 Datasheet, PDF (77/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 4 Exception Handling
Section 4 Exception Handling
4.1 Overview
4.1.1 Exception Handling Types and Priorities
As figure 4.1 indicates, exception handling may be caused by a reset, address error, interrupt, or
instruction. Exception sources are prioritized as indicated in figure 4.1. If two or more exceptions
occur simultaneously, they are accepted and handled in the priority order shown.
Rev. 7.00 Jan 31, 2006 page 51 of 658
REJ09B0272-0700