SH7032 Datasheet, PDF (386/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Serial Communication Interface (SCI)
Bits 1 and 0—Clock Select 1 and 0 (CKS1 and CKS0): CKS1 and CKS0 select the internal
clock source of the on-chip baud rate generator. Four clock sources are available: φ, φ/4, φ/16, and
φ/64. For further information on the clock source, bit rate register settings, and baud rate, see
section 13.2.8, Bit Rate Register (BRR).
Bit 1: CKS1
0
1
Bit 0: CKS0
0
1
0
1
Description
System clock (φ)
φ/4
φ/16
φ/64
(Initial value)
13.2.6 Serial Control Register
The serial control register (SCR) enables the SCI transmitter/receiver, selects serial clock output in
asynchronous mode, enables and disables interrupts, and selects the transmit/receive clock source.
The CPU can always read and write to SCR. SCR is initialized to H'00 by a reset and in standby
mode.
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE
MPIE TEIE CKE1 CKE0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W
Bit 7—Transmit Interrupt Enable (TIE): TIE enables or disables the transmit-data-empty
interrupt (TXI) requested when the transmit data register empty bit (TDRE) in the serial status
register (SSR) is set to 1 due to transfer of serial transmit data from TDR to TSR.
Bit 7: TIE
0
1
Description
Transmit-data-empty interrupt request (TXI) is disabled
(Initial value)
The TXI interrupt request can be cleared by reading TDRE after it has been set
to 1, then clearing TDRE to 0, or by clearing TIE to 0.
Transmit-data-empty interrupt request (TXI) is enabled
Rev. 7.00 Jan 31, 2006 page 360 of 658
REJ09B0272-0700