SH7032 Datasheet, PDF (272/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
Bits 6 and 5—Counter Clear 1 and 0 (CCLR1 and CCLR0): CCLR1 and CCLR0 select the
counter clear source.
Bit 6: Bit 5:
CCLR1 CCLR0 Description
0
0
TCNT is not cleared
(Initial value)
1
TCNT is cleared by general register A (GRA) compare match or input
capture*¹
1
0
TCNT is cleared by general register B (GRB) compare match or input
capture*¹
1
Synchronizing clear: TCNT is cleared in synchronization with clear of other
timer counters operating in sync*²
Notes: 1. When GR is functioning as an output compare register, TCNT is cleared upon a
compare match. When functioning as an input capture register, TCNT is cleared upon
input capture.
2. The timer synchro register (TSNC) sets the synchronization.
Bits 4 and 3—External Clock Edge 1/0 (CKEG1 and CKEG0): CKEG1 and CKEG0 select
external clock input edge. When channel 2 is set for phase counting mode, settings of the CKEG1
and CKEG0 bits in TCR are ignored and the phase counting mode operation takes priority.
Bit 4: Bit 3:
CKEG1 CKEG0
0
0
1
1
—
Description
Count rising edges
Count falling edges
Count both rising and falling edges
(Initial value)
Rev. 7.00 Jan 31, 2006 page 246 of 658
REJ09B0272-0700