SH7032 Datasheet, PDF (114/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 6 User Break Controller (UBC)
6.2.3 Break Bus Cycle Register (BBR)
The break bus cycle register (BBR) is a 16-bit read/write register that selects the following four
break conditions:
• CPU cycle or DMA cycle
• Instruction fetch or data access
• Read or write
• Operand size (byte, word, longword)
A reset initializes BBR to H'0000. It is not initialized in standby mode.
Bit
Initial value
Read/Write
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
CD1
CD0
ID1
ID0
RW1 RW0
SZ1
SZ0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W
Bits 15–8—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 7 and 6—CPU Cycle/DMA Cycle Select (CD1 and CD0): CD1 and CD0 select whether to
break on CPU and/or DMA bus cycles.
Bit 7: CD1
0
1
Bit 6: CD0
0
1
0
1
Description
No break interrupt occurs
Break only on CPU cycles
Break only on DMA cycles
Break on both CPU and DMA cycles
(Initial value)
Rev. 7.00 Jan 31, 2006 page 88 of 658
REJ09B0272-0700