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SH7032 Datasheet, PDF (233/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer
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Section 9 Direct Memory Access Controller (DMAC)
Table 9.6 Relationship of Request Modes and Bus Modes by DMA Transfer Category
Address
Mode Transfer Category
Request
Mode
Bus
Mode
Transfer
Size
(bits)
Usable
Channels
Single External device with DACK and
External B/C
8/16
0,1
external memory
Dual
External device with DACK and
memory-mapped external device
External memory and external
memory
External memory and memory-
mapped external device
Memory-mapped external device and
memory-mapped external device
External memory and on-chip
memory
External memory and on-chip
supporting module
Memory-mapped external device and
on-chip memory
Memory-mapped external device and
on-chip supporting module
On-chip memory and on-chip
memory
On-chip memory and on-chip
supporting module
On-chip supporting module and on-
chip supporting module
External
All*1
All*1
All*1
All*1
All*2
All*1
All*2
All*1
All*2
All*2
B/C
B/C
B/C
B/C
B/C
B/C*3
B/C
B/C*3
B/C
B/C*3
B/C*3
8/16
8/16
8/16
8/16
8/16
8/16*4
8/16
8/16*4
8/16
8/16*4
8/16*4
0, 1
0–3*5
0–3*5
0–3*5
0–3*5
0–3*5
0–3*5
0–3*5
0–3*5
0–3*5
0–3*5
B: Burst, C: Cycle steal
Notes: 1. External requests, auto requests and on-chip supporting module requests are all
available. For on-chip supporting module requests, however, SCI and A/D converter
cannot be specified as the transfer request source.
2. External requests, auto requests and on-chip supporting module requests are all
available. When the SCI or A/D converter is also the transfer request source, however,
the transfer destination or transfer source must be the SCI or A/D converter,
respectively.
3. If the transfer request source is the SCI, cycle-steal only.
4. The access size permitted when the transfer destination or source is an on-chip
supporting module register.
5. If the transfer request is an external request, channels 0 and 1 only.
Rev. 7.00 Jan 31, 2006 page 207 of 658
REJ09B0272-0700
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