SH7032 Datasheet, PDF (531/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

CK
A21–A0
RAS
CAS
RD(Read)
Section 20 Electrical Characteristics
T_p
T_r
T_c
T_c
T_c
T_c
t_AD
t_AD
Row address Column address Column address Column address
Column address
t_RASD1
t_RASD2
t_ASC t_CP
t_RDD
t_RSD
WRH, WRL,
WR(Read)
AD15–AD0
DPH, DPL
(Read)
DACK0
DACK1
(Read)
t_CAC1^{*1 tACP}
t_RAC1^{*3 tACC1*2 tRDS tRDH*4}
t_DACD1 t_DACD2
t_RDH*⁵
Notes: 1. For t_CAC1, use t_cyc × 0.65 – 35 (for 35% duty) or tcyc × 0.5 – 35 (for 50% duty) instead of
tcyc – t_AD – t_ASC – t_RDS.
It is not necessary to meet the t_RDS specification as long as the t_CAC1 specification is met.
2. For t_ACC1, use t_cyc – 44 instead of t_cyc – t_AD – t_RDS.
It is not necessary to meet the t_RDS specification as long as the t_ACC1 specification is met.
3. For t_RAC1, use t_cyc × 1.5 – 35 instead of t_cyc × 1.5 – t_RASD1 – t_RDS.
It is not necessary to meet the t_RDS specification as long as the t_RAC1 specification is met.
4. t_RDH is measured from A21–A0 or CAS, whichever is negated first.
5. t_RDH is measured from A21–A0, RAS, or CAS, whichever is negated first.
Figure 20.25 (a) DRAM Bus Cycle (Short-Pitch, High-Speed Page Mode: Read)
Rev. 7.00 Jan 31, 2006 page 505 of 658
REJ09B0272-0700