SH7032 Datasheet, PDF (359/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 11 Programmable Timing Pattern Controller (TPC)
TPC Output Non-Overlap Operation (Four-Phase Complementary Non-Overlap Output)
(Figure 11.7):
1. Set the GRA and GRB registers of the ITU that serves as output triggers as output compare
registers. Set the cycle in GRB and the non-overlap cycle time in GRA and select counter
clearing upon compare match B. Set the IMIEA bit in TIER to 1 to enable the IMIA interrupt.
2. Write H'FFFF in PBCR1, write H'FF in NDERB, and set G3CMS1, G3CMS0, G2CMS1, and
G2CMS0 in TPCR to set the ITU compare match selected in step 1 as the output trigger. Set
the G3NOV and G2NOV bits in TPMR to 1 to set non-overlap operation. Write output data
H'95 in NDRB.
3. When the selected ITU channel starts operating and a GRB compare match occurs, 1 output
changes to 0 output; when a GRA compare match occurs, 0 output changes to 1 output. (The
change from 0 output to 1 output is delayed by the value set in GRA.) The IMIA interrupt
handling routine writes the next output data (H'65) in NDRB.
4. Four-phase complementary non-overlap output can be obtained by writing H'59, H'56, H'95…
at successive IMIA interrupts. If the DMA controller is set for activation by compare match,
pulse output can be obtained without imposing a load on the CPU.
Rev. 7.00 Jan 31, 2006 page 333 of 658
REJ09B0272-0700