SH7032 Datasheet, PDF (263/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
Bit 0—Timer Synchro 0 (SYNC0): SYNC0 selects synchronizing mode for channel 0.
Bit 0: SYNC0
0
1
Description
The timer counter for channel 0 (TCNT0) operates independently (Preset/clear
of TCNT0 is independent of other channels)
(Initial value)
Channel 0 operates synchronously. Synchronized preset/clear of TNCT0
enabled.
10.2.3 Timer Mode Register (TMDR)
The timer mode register (TMDR) is an eight-bit read/write register that selects PWM mode for
channels 0–4, sets phase counting mode for channel 2, and sets the conditions for the overflow
flag (OVF). TMDR is initialized to H'80 or H'00 by a reset and in standby mode.
Bit
7
—
Initial value
*
Read/Write
—
Note: * Undefined
6
MDF
0
R/W
5
FDIR
0
R/W
4
PWM4
0
R/W
3
PWM3
0
R/W
2
PWM2
0
R/W
1
PWM1
0
R/W
0
PWM0
0
R/W
Bit 7—Reserved: Bit 7 is read as undefined. The write value should be 0 or 1.
Bit 6—Phase Counting Mode (MDF): MDF selects phase counting mode for channel 2.
Bit 6: MDF
0
1
Description
Channel 2 operates normally
Channel 2 operates in phase counting mode
(Initial value)
When the MDF bit is set to 1 to select phase counting mode, the timer counter (TCNT2) becomes
an up/down-counter and the TCLKA and TCLKB pins become count clock input pins. TCNT2
counts on both the rising and falling edges of TCLKA and TCLKB, with increment/decrement
chosen as follows:
Count
Direction
TCLKA pin
TCLKB pin
Decrement
Rising High
Low
Rising
Falling Low
High Falling
Increment
Rising High
High Falling
Falling
Low
Low
Rising
Rev. 7.00 Jan 31, 2006 page 237 of 658
REJ09B0272-0700