SH7032 Datasheet, PDF (199/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Bus State Controller (BSC)
The low width of RAS output may be shorter than usual in a reset (2.5 tcyc → 1.5 tcyc),
preventing the specified value (t_RAS) of DRAM from being satisfied.
Corresponding DRAM conditions: Long-pitch/normal mode
Long-pitch/high-speed page mode
There are no problems regarding operations except for the above conditions.
There are the following four cases (figures 8.38 to 8.41) for the output states of DRAM control
signals (RAS, CAS, and WR) corresponding to RES latch timing. Actual output levels are shown
by solid lines (not by dashed lines).
CK
RES
A0–A21
RAS
CAS
WR
AD0–AD15
RES latch
Tp
timing
Tr
Tc1
Tc2
Manual reset
Row address Column address FFFF
Data output
Figure 8.38 Long-Pitch Mode Write (1)
RES latch
timing
CK
Tp
Tr
Tc1
Tc2
RES
Manual reset
A0–A21
Row address FFFF
RAS
CAS
WR
AD0–AD15
Data output
Figure 8.39 Long-Pitch Mode Write (2)
Rev. 7.00 Jan 31, 2006 page 173 of 658
REJ09B0272-0700