SH7032 Datasheet, PDF (337/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
Register Setting
TSNC
TMDR
TFCR
TOCR
TIOR4
TCR4
Reset
Output
Operating
Comp Sync
Level
Mode
Sync MDF FDIR PWM PWM PWM Buffer Select IOA
IOB
Clear Clock
Select Select
Comple- √*²
—— —
CMD1 CMD1 √
√
—
—
mentary
=1 =1
PWM
CMD0 CMD0
=0 =0
Reset
√
—— —
CMD1 CMD1 √
√
—
—
synchron-
=1 =1
ized PWM
CMD0 CMD0
=1 =1
CCLR1 √*⁴
=0
CCLR0
=0
√*⁵
√*⁵
Buffer
√
—— √
√
√
BFA4 —
√
√
(BRA)
= 1,
others:
don’t
care
√
√
Buffer
√
—— √
√
√
BFB4 —
√
√
(BRB)
= 1,
others:
don’t
care
√
√
√: Settable, —: Setting does not affect current mode
Notes: 1. In PWM mode, the input capture function cannot be used. When compare match A and
compare match B occur simultaneously, the compare match signal is inhibited.
2. When set for complementary PWM mode, do not simultaneously set channel 3 and
channel 4 to function synchronously.
3. Counter clearing works with reset-synchronized PWM mode, but TCNT4 runs
independently. The output waveform is not affected.
4. Clock selection when complementary PWM mode is set should be the same for
channels 3 and 4.
5. In reset-synchronized PWM mode, TCNT4 runs independently. The output waveform is
not affected.
Rev. 7.00 Jan 31, 2006 page 311 of 658
REJ09B0272-0700