SH7032 Datasheet, PDF (230/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 9 Direct Memory Access Controller (DMAC)
External data bus
SuperH microcomputer
2
DMAC
External
memory
External
memory
1
: Data flow
1: Read cycle
2: Write cycle
Figure 9.8 Data Flow in Dual Address Mode
In dual address mode transfers, external memory, memory-mapped external devices, on-chip
memory and on-chip supporting modules can be mixed without restriction. Specifically, this
enables the following transfer types:
1. Between external memory and a external memory
2. Between external memory and a memory-mapped external device
3. Between a memory-mapped external devices
4. Between external memory and on-chip memory
5. Between external memory and an on-chip supporting module (excluding the DMAC)
6. Between memory-mapped external device and on-chip memory
7. Between memory-mapped external device and an on-chip supporting module (excluding the
DMAC)
8. On-chip memory to on-chip memory
9. Between on-chip memory and an on-chip supporting module (excluding the DMAC)
10. Between on-chip supporting modules (excluding the DMAC)
Transfer requests can be auto requests, external requests, or on-chip supporting module requests.
When the transfer request source is either the SCI or A/D converter, however, either the data
destination or source must be the SCI or A/D converter (table 9.4). In dual address mode, DACK
is output in read or write cycles other than for internal memory and external supporting modules.
CHCR controls the cycle in which DACK is output.
Figure 9.9 shows the DMA transfer timing in dual address mode.
Rev. 7.00 Jan 31, 2006 page 204 of 658
REJ09B0272-0700