SH7032 Datasheet, PDF (284/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
Counting mode selection
Select counter clock
(1)
Counting?
No
Yes
Periodic counter
Select counter
clear source
(2)
Select output
compare register
(3)
Free-running counter
Set period
(4)
Start counting
(5)
Start counting
(5)
Periodic counter
Free-running counter
Figure 10.14 Procedure for Selecting the Counting Mode
• Free-running count and periodic count
A reset of the counters for channels 0–4 leaves them all in free-running mode. When a
corresponding bit in TSTR is set to 1, the corresponding timer counter operates as a free-
running counter and begins to increment. When the count wraps around from H'FFFF to
H'0000, the overflow flag (OVF) in the timer status register (TSR) is set to 1. If the OVIE bit
in the timer's corresponding interrupt enable register (TIER) is set to 1, an interrupt request
will be sent to the CPU. After TCNT overflows, counting continues from H'0000. Figure 10.15
shows an example of free-running counting.
Periodic counter operation is obtained for a given channel's TCNT by selecting compare match
as a TCNT clear source. (Set GRA or GRB for period setting to output compare register and
select counter clear upon compare match using the CCLR1 and CCLR0 bits in the timer
control register (TCR).) After setting, TCNT begins incrementing as a periodic counter when
the corresponding bit in TSTR is set to 1. When the count matches GRA or GRB, the
IMFA/IMFB bit in TSR is set to 1 and the counter is automatically cleared to H'0000. If the
IMIEA/IMIEB bit of the corresponding TIER is set to 1 at this point, an interrupt request will
be sent to the CPU. After the compare match, TCNT continues counting from H'0000. Figure
10.16 shows an example of periodic counting.
Rev. 7.00 Jan 31, 2006 page 258 of 658
REJ09B0272-0700