SH7032 Datasheet, PDF (50/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 2 CPU
2.3.2 Addressing Modes
Addressing modes and effective address calculation are described in table 2.8.
Table 2.8 Addressing Modes and Effective Addresses
Addressing Mnemonic
Mode
Expression
Direct
Rn
register
addressing
Indirect
register
addressing
@Rn
Post-incre-
ment
indirect
register
addressing
@Rn +
Pre-decre-
ment
indirect
register
addressing
@–Rn
Effective Addresses Calculation
The effective address is register Rn. (The operand
is the contents of register Rn.)
Equation
—
The effective address is the contents of register Rn. Rn
Rn
Rn
The effective address is the contents of register Rn. Rn
A constant is added to the contents of Rn after the
instruction is executed. 1 is added for a byte
operation, 2 for a word operation, and 4 for a
longword operation.
(After the
instruction is
executed)
Byte: Rn + 1
Rn
Rn
→ Rn
Rn + 1/2/4 ₊
Word: Rn + 2
→ Rn
1/2/4
Longword:
Rn + 4 → Rn
The effective address is the value obtained by
subtracting a constant from Rn. 1 is subtracted for
a byte operation, 2 for a word operation, and 4 for a
longword operation.
Byte: Rn – 1
→ Rn
Word: Rn – 2
→ Rn
Rn
Rn – 1/2/4 _–
1/2/4
Rn – 1/2/4
Longword:
Rn – 4 → Rn
(Instruction
executed
with Rn after
calculation)
Rev. 7.00 Jan 31, 2006 page 24 of 658
REJ09B0272-0700