SH7032 Datasheet, PDF (236/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 9 Direct Memory Access Controller (DMAC)
CK
DREQ
Bus cycle
CPU CPU CPU DMAC (R) DMAC (W) CPU CPU CPU
DACK
DMAC (R): DMAC read cycle
DMAC (W): DMAC write cycle
Note: Illustrates the case when DACK is output during the DMAC read cycle.
Figure 9.14 DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ Level
Detection and DACK Active-Low) (Dual Address Mode, Bus Cycle = 1 State)
CK
DREQ
Bus cycle
CPU CPU CPU DMAC CPU CPU CPU CPU
DACK
Figure 9.15 DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ Level
Detection and DACK Active-Low) (Single Address Mode, Bus Cycle = 2 States)
Rev. 7.00 Jan 31, 2006 page 210 of 658
REJ09B0272-0700