SH7032 Datasheet, PDF (492/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 19 Power-Down State
19.1.2 Register
Table 19.2 summarizes the register related to the power-down state.
Table 19.2 Standby Control Register (SBYCR)
Name
Abbreviation R/W Initial Value Address* Access size
Standby control register SBYCR
R/W H'1F
H'5FFFFBC 8, 16, 32
Note: * Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For details
on the register addresses, see section 8.3.5, Area Descriptions.
19.2 Standby Control Register (SBYCR)
The standby control register (SBYCR) is an 8-bit read/write register. It is used to enter standby
mode and also sets the port states in standby mode. SBYCR is initialized to H'1F by a reset.
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
SBY
HIZ
—
—
—
—
—
—
0
0
0
1
1
1
1
1
R/W R/W
—
—
—
—
—
—
Bit 7Standby (SBY): SBY enables transition to standby mode. The SBY bit cannot be set to 1
while the timer enable bit (bit TME) in timer control/status register TCSR of the watchdog timer
(WDT) is set to 1. To enter standby mode, clear the TME bit to 0 to halt the WDT and then set the
SBY bit.
SBY
0
1
Description
Executing SLEEP instruction puts the chip into sleep mode
Executing SLEEP instruction puts the chip into standby mode
(Initial value)
Bit 6Port High-Impedance (HIZ): HIZ selects whether I/O ports remain in their previous
states during standby, or are placed in the high-impedance state when standby mode is entered.
The HIZ bit cannot be set to 1 while the TME bit is set to 1. To place the pins of the I/O ports in
high impedance, clear the TME bit to 0 before setting the HIZ bit.
HIZ
Description
0
Port states are maintained during standby
(Initial value)
1
Ports are placed in the high-impedance state in standby
Rev. 7.00 Jan 31, 2006 page 466 of 658
REJ09B0272-0700