SH7032 Datasheet, PDF (340/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 11 Programmable Timing Pattern Controller (TPC)
11.1.2 Block Diagram
Figure 11.1 shows a block diagram of the TPC.
ITU compare match signal
Control logic
PBCR1
NDERA
TPMR
PBCR2
NDERB
TPCR
TP15
TP14
TP13
TP12
TP11
TP10
TP9
TP8
TP7
TP6
TP5
TP4
TP3
TP2
TP1
TP0
Pulse output
pin group 3
Pulse output
pin group 2
Pulse output
pin group 1
Pulse output
pin group 0
PBDR
NDRB
NDRA
TPC
TPMR: TPC output mode register
TPCR: TPC output control register
NDERB: Next data enable register
NDERA: Next data enable register
PBCR1: Port B control register 1
PBCR2: Port B control register 2
B NDRB: Next data register B
A NDRA: Next data register A
PBDR: Port B data register
Figure 11.1 Block Diagram of TPC
Internal
data
bus
Rev. 7.00 Jan 31, 2006 page 314 of 658
REJ09B0272-0700