SH7032 Datasheet, PDF (479/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 17 ROM
Section 17 ROM
17.1 Overview
The SH7034 microcomputer has 64 kbytes of on-chip ROM (mask ROM or PROM). The on-chip
ROM is connected to the CPU and the direct memory access controller (DMAC) through a 32-bit
data bus (figure 17.1). The CPU can access the on-chip ROM in 8-, 16- and 32-bit widths and the
DMAC can access the ROM in 8- and 16-bit widths. Data in the on-chip ROM can always be
accessed in one cycle.
Internal data bus (32 bits)
H'0000000
H'0000004
H'0000001
H'0000005
H'0000002
H'0000006
H'0000003
H'0000007
On-chip ROM
H'000FFFC
H'000FFFD
H'000FFFE
H'000FFFF
Note: The addresses shown in the figure are the uppermost shadow addresses in the on-chip
ROM space.
Figure 17.1 Block Diagram of ROM
The operating mode determines whether the on-chip ROM is valid or not. The operating mode is
selected using mode-setting pins MD0–MD2 as shown in table 17.1. When using the on-chip
ROM, select mode 2; otherwise, select mode 0 or 1. The on-chip ROM is allocated to addresses
H'0000000–H'000FFFF of memory area 0. Memory area 0 (H'0000000–H'0FFFFFF and
H'8000000–H'8FFFFFF) is divided into 64-kbyte shadows. No matter which shadow is accessed,
the on-chip ROM is accessed. See section 8, Bus State Controller (BSC), for more information on
shadows.
Rev. 7.00 Jan 31, 2006 page 453 of 658
REJ09B0272-0700