SH7032 Datasheet, PDF (629/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
A.2.33 Interrupt Priority Setting Register E (IPRE)
INTC
Start Address: H'5FFFF8C
Bus Width: 8/16/32
Bit
15
14
13
12
11
10
9
8
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
—
—
—
—
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
—
—
—
—
Table A.34 IPRE Bit Functions
Bit
Bit name
Description
15–12
11–8
7–4
(Set SCI1 priority level)
(Set PRT*¹ and A/D priority levels)
(Set WDT and REF*² priority
levels)
Sets the SC1 priority level value
Sets the PRT*¹ and A/D priority level values
Sets the WDT and REF*² priority level value
Notes
1. PRT: Parity control section within the bus state controller. See section 8, Bus State
Controller (BSC), for more information.
2. REF: DRAM refresh control section within the bus state controller. See section 8, Bus
State Controller (BSC), for more information.
Rev. 7.00 Jan 31, 2006 page 603 of 658
REJ09B0272-0700