SH7032 Datasheet, PDF (107/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 5 Interrupt Controller (INTC)
Interrupt accepted
5 + m1 + m2 + m3
3
3 m1 m2 1 m3 1
IRQ
Instruction (instruction replaced by
interrupt exception handling)
F DE E MMEME E
Overrun fetch
F
Interrupt service routine—
first instruction
(edge)
IRQOUT
(level)
FDE
When m1 = m2 = m3, the interrupt response time is 11 cycles.
F (Instruction fetch)
D (Instruction decoding)
E (Instruction execution)
M (Memory access)
Instruction fetched from memory where program is stored.
The fetched instruction is decoded.
Data operations and address calculations are performed
according to the decoded results.
Data in memory is accessed.
Note: For the interrupt acceptance timing, see table 4.1, Exception Source Detection and
Start of Handling, in section 4.1.2, Exception Handling Operation.
Figure 5.4 Example of Pipelining in IRQ Interrupt Acceptance
5.6 Usage Notes
When the following operations are performed in the order shown when a pin to which IRQ input is
assigned is designated as a general input pin by the pin function controller (PFC) and inputs a low-
level signal, the IRQ falling edge is detected, and an interrupt request is detected, immediately
after the setting in (b) is performed:
• An interrupt control register (ICR) setting is made so that an interrupt is detected at the falling
edge of IRQ. …(a)
• The function of pins to which IRQ input is assigned is switched from general input to IRQ
input by a pin function controller (PFC) setting. …(b)
Therefore, when switching the pin function from general input pin to IRQ input, the pin function
controller (PFC) setting should be changed to IRQ input while the pin to which IRQ input is
assigned is high.
Rev. 7.00 Jan 31, 2006 page 81 of 658
REJ09B0272-0700