SH7032 Datasheet, PDF (60/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 2 CPU
Table 2.12 Data Transfer Instructions
Instruction
MOV #imm,Rn
MOV.W @(disp,PC),Rn
MOV.L @(disp,PC),Rn
MOV Rm,Rn
MOV.B Rm,@Rn
MOV.W Rm,@Rn
MOV.L Rm,@Rn
MOV.B @Rm,Rn
MOV.W @Rm,Rn
MOV.L @Rm,Rn
MOV.B Rm,@–Rn
MOV.W Rm,@–Rn
MOV.L Rm,@–Rn
MOV.B @Rm+,Rn
MOV.W @Rm+,Rn
MOV.L @Rm+,Rn
MOV.B R0,@(disp,Rn)
MOV.W R0,@(disp,Rn)
MOV.L Rm,@(disp,Rn)
MOV.B @(disp,Rm),R0
Instruction Code
1110nnnniiiiiiii
1001nnnndddddddd
1101nnnndddddddd
0110nnnnmmmm0011
0010nnnnmmmm0000
0010nnnnmmmm0001
0010nnnnmmmm0010
0110nnnnmmmm0000
0110nnnnmmmm0001
0110nnnnmmmm0010
0010nnnnmmmm0100
0010nnnnmmmm0101
0010nnnnmmmm0110
0110nnnnmmmm0100
0110nnnnmmmm0101
0110nnnnmmmm0110
10000000nnnndddd
10000001nnnndddd
0001nnnnmmmmdddd
10000100mmmmdddd
Operation
#imm → Sign extension
→ Rn
(disp × 2 + PC) → Sign
extension → Rn
(disp × 4 + PC) → Rn
Rm → Rn
Rm → (Rn)
Rm → (Rn)
Rm → (Rn)
(Rm) → Sign extension
→ Rn
(Rm) → Sign extension
→ Rn
(Rm) → Rn
Rn–1 → Rn, Rm → (Rn)
Rn–2 → Rn, Rm → (Rn)
Rn–4 → Rn, Rm → (Rn)
(Rm) → Sign extension
→ Rn, Rm + 1 → Rm
(Rm) → Sign extension
→ Rn, Rm + 2 → Rm
(Rm) → Rn, Rm + 4 →
Rm
R0 → (disp + Rn)
R0 → (disp × 2 + Rn)
Rm → (disp × 4 + Rn)
(disp + Rm) → Sign
extension → R0
Execu-
tion
Cycles
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
T Bit
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Rev. 7.00 Jan 31, 2006 page 34 of 658
REJ09B0272-0700