SH7032 Datasheet, PDF (329/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
10.6.11 Note on Writing in Synchronizing Mode
After synchronizing mode is selected, if TCNT is written by byte access, all 16 bits of all
synchronized counters assume the same value as the counter that was addressed.
Example: Figures 10.67 and 10.68 show byte write and word write when channels 2 and 3 are
synchronized
Write A to upper
TCNT2
W
X
byte of channel 2 _TCNT2
A
X
TCNT3
Y
Upper
byte
Z
Lower
byte
Write A to lower
byte of channel 3
TCNT3
TCNT2
A
Upper
byte
Y
X
Lower
byte
A
TCNT3
Y
Upper
byte
A
Lower
byte
Figure 10.67 Byte Write to Channel 2 or Byte Write to Channel 3
TCNT2
W
X
TCNT2
A
B
TCNT3
Y
Upper
byte
Z
Lower
byte
Word write of AB TCNT3
for channel 2 or 3
A
Upper
byte
B
Lower
byte
Figure 10.68 Word Write to Channel 2 or Word Write to Channel 3
10.6.12 Note on Setting Reset-Synchronized PWM Mode/Complementary PWM Mode
When the CMD1 and CMD0 bits in TFCR are set, note the following.
1. Writes to CMD1 and CMD0 should be carried out while TCNT3 and TCNT4 are halted.
2. Changes of setting from reset-synchronized PWM mode to complementary PWM mode and
vice versa are prohibited. Set reset-synchronized PWM mode or complementary PWM mode
after first setting normal operation (clear CMD1 bit to 0).
Rev. 7.00 Jan 31, 2006 page 303 of 658
REJ09B0272-0700