SH7032 Datasheet, PDF (102/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 5 Interrupt Controller (INTC)
Bits 7–0IRQ0–IRQ7 Sense Select (IRQ0S–IRQ7S): IRQ0–IRQ7 select whether the falling
edge or low level of the IRQ inputs is sensed at pins IRQ0–IRQ7.
Bits 7–0:
IRQ0S–IRQ7S
0
1
Description
Interrupt is requested when IRQ input is low
Interrupt is requested on falling edge of IRQ input
(Initial value)
5.4 Interrupt Operation
5.4.1 Interrupt Sequence
The sequence of interrupt operations is described below. Figure 5.2 shows a flowchart of the
operations up to acceptance of the interrupt.
1. The interrupt request sources send interrupt request signals to the interrupt controller.
2. The interrupt controller selects the highest-priority interrupt among the interrupt requests sent,
following the priority order indicated in table 5.3 and the levels set in interrupt priority
registers A–E (IPRA–IPRE). Lower priority interrupts are ignored*. If two interrupts with the
same priority level are requested simultaneously, or if there are multiple interrupts occurring
within a single module, the interrupt with the highest default priority or priority within module
as indicated in table 5.3 is selected.
3. The interrupt controller compares the priority level of the selected interrupt request with the
interrupt mask level bits (I3–I0) in the CPU’s status register (SR). If the request priority level
is equal to or less than the interrupt mask level, the request is ignored. If the request priority
level is higher than the interrupt mask level, the interrupt controller accepts the request and
sends an interrupt request signal to the CPU.
4. When the interrupt controller accepts an interrupt request, it drives IRQOUT pin low.
5. The CPU detects the interrupt request sent from the interrupt controller when it decodes the
next instruction to be executed. Instead of executing that instruction, the CPU starts interrupt
exception handling. (See figure 5.4.)
6. In interrupt exception handling, first SR and PC are pushed onto the stack.
7. The priority level of the accepted interrupt is copied to the interrupt mask level bits (I3–I0) in
the status register (SR).
8. When the accepted interrupt is level-sensed or from an on-chip supporting module, the
IRQOUT pin returns to the high level. If the accepted interrupt is edge-sensed, the IRQOUT
pin returns to the high level when the instruction to be executed by the CPU in (5) is replaced
by the interrupt exception handling. If the interrupt controller has accepted another interrupt
(of a level higher than the current interrupt), however, the IRQOUT pin remains low.
Rev. 7.00 Jan 31, 2006 page 76 of 658
REJ09B0272-0700