SH7032 Datasheet, PDF (84/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 4 Exception Handling
4.3 Address Errors
4.3.1 Address Error Sources
Address errors occur during instruction fetches and data reading/writing as shown in table 4.5.
Table 4.5 Address Error Sources
Bus Cycle
Type
Bus Master
Operation
Address Error
Instruction fetch CPU
Instruction fetch from even address
None (normal)
Instruction fetch from odd address
Address error
Instruction fetch from outside on-chip
supporting module space
Instruction fetch from on-chip supporting
module space
None (normal)
Address error
Data read/write CPU or DMAC Access to word data from even address None (normal)
Access to word data from odd address
Access to longword data aligned on
longword boundary
Address error
None (normal)
Access to longword data not aligned on
longword boundary
Access to word or byte data in on-chip
supporting module space*
Address error
None (normal)
Access to longword data in 16-bit on-
chip supporting module space*
Access to longword data in 8-bit on-chip
supporting module space*
None (normal)
Address error
Note: * See section 8, Bus State Controller (BSC), for details on the on-chip supporting module
space.
4.3.2 Address Error Exception Handling
When an address error occurs, address error exception handling starts after both the bus cycle that
caused the address error and the instructions that were being executed at that time, have been
completed. The CPU then:
1. Pushes SR onto the stack.
2. Pushes the program counter onto the stack. The PC value saved is the start address of the
instruction following the last instruction to be executed.
3. Fetches the exception handling routine start address from the exception vector table for the
address error that occurred and starts program execution from that address. The branch that
occurs here is not a delayed branch.
Rev. 7.00 Jan 31, 2006 page 58 of 658
REJ09BX0272-0700