SH7032 Datasheet, PDF (267/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
Bit 0—Buffer Mode A3 (BFA3): BFA3 selects buffer mode for GRA3 and BRA3 in channel 3.
Bit 0: BFA3
0
1
Description
GRA3 operates normally in channel 3
GRA3 and BRA3 operate in buffer mode in channel 3
(Initial value)
10.2.5 Timer Output Control Register (TOCR)
The timer output control register (TOCR) is an eight-bit read/write register that inverts the output
level in complementary PWM mode/reset-synchronized PWM mode. Setting bits OLS3 and OLS4
is valid only in complementary PWM mode and reset-synchronized PWM mode. In other output
situations, these bits are ignored. TOCR is initialized to H'FF or H'7F by a reset and in standby
mode.
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
—
OLS4 OLS3
Initial value
*
1
1
1
1
1
1
1
Read/Write
—
—
—
—
—
—
R/W
R/W
Note: * Undefined
Bits 7–2—Reserved: Bit 7 is read as undefined. Bits 6–2 are always read as 1. The write value to
bit 7 should be 0 or 1. The write value to bits 6–2 should always be 1.
Bit 1—Output Level Select 4 (OLS4): OLS4 selects the output level for complementary PWM
mode or reset-synchronized PWM mode.
Bit 1: OLS4
0
1
Description
TIOCA3, TIOCA4, and TIOCB4 are inverted and output
TIOCA3, TIOCA4, and TIOCB4 are output directly
(Initial value)
Bit 0—Output Level Select 3 (OLS3): OLS3 selects the output level for complementary PWM
mode or reset-synchronized PWM mode.
Bit 0: OLS3
0
1
Description
TIOCB3, TOCXA4, and TOCXB4 are inverted and output
TIOCB3, TOCXA4, and TOCXB4 are output directly
(Initial value)
Rev. 7.00 Jan 31, 2006 page 241 of 658
REJ09B0272-0700