SH7032 Datasheet, PDF (347/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 11 Programmable Timing Pattern Controller (TPC)
Address H'5FFFFF6
Bits 7–0—Reserved: These bits are always read as 1. The write value should always be 1.
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
1
1
1
1
1
1
1
1
—
—
—
—
—
—
—
—
Different Triggers for TPC Output Groups 3 and 2: If TPC output groups 3 and 2 are triggered
by different compare matches, the address of the upper 4 bits of NDRB (group 3) is H'5FFFFF4
and the address of the lower 4 bits of NDRB (group 2) is H'5FFFFF6. Bits 3–0 of address
H'5FFFFF4 and bits 7–4 of address H'5FFFFF6 are reserved bits. These bits are always read as 1.
The write value should always be 1.
Address H'5FFFFF4
Bits 7–4—Next Data 15–12 (NDR15–NDR12): NDR15–NDR12 store the next output data for
TPC output group 3.
Bits 3–0—Reserved: These bits are always read as 1. The write value should always be 1.
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
NDR15 NDR14 NDR13 NDR12 —
—
—
—
0
0
0
0
1
1
1
1
R/W
R/W
R/W
R/W
—
—
—
—
Address H'5FFFFF6
Bits 7–4—Reserved: These bits are always read as 1. The write value should always be 1.
Bits 3–0—Next Data 11–8 (NDR11–NDR8): NDR11–NDR8 store the next output data for TPC
output group 2.
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
—
—
—
— NDR11 NDR10 NDR9 NDR8
1
1
1
1
0
0
0
0
—
—
—
—
R/W
R/W
R/W
R/W
Rev. 7.00 Jan 31, 2006 page 321 of 658
REJ09B0272-0700