SH7032 Datasheet, PDF (232/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 9 Direct Memory Access Controller (DMAC)
• Burst Mode
Once the bus is obtained, the transfer is performed continuously until the transfer end
condition is satisfied. In external request mode with low-level detection at the DREQ pin,
however, when the DREQ pin is driven high, the bus passes to the other bus master after the
bus cycle of the DMAC that currently has an acknowledged request ends, even if the transfer
end conditions have not been satisfied.
Burst mode cannot be used when the serial communication interface (SCI) is the transfer
request source. Figure 9.11 shows an example of DMA transfer timing in burst mode. The
transfer conditions shown in the figure are:
 Single address mode
 DREQ level detection
DREQ
Bus cycle CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC CPU
Figure 9.11 Transfer Example in Burst Mode (Single Address Mode, DREQ Level
Detection)
Relationship between Request Modes and Bus Modes by DMA Transfer Category: Table 9.6
shows the relationship between request modes and bus modes by DMA transfer category.
Rev. 7.00 Jan 31, 2006 page 206 of 658
REJ09B0272-0700