PIC18LF24K Datasheet, PDF (9/594 Pages) –

TABLE 2: 40/44-PIN ALLOCATION TABLE (PIC18(L)F45/46K40)
I/O⁽²⁾
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
RC0
RC1
Note
2
17
19
19 ANA0
—
C1INO-
—
—
—
—
IOCA0
—
—
C2IN0-
—
Y
—
3
18
20
20 ANA1
—
C1IN1-
—
—
—
—
IOCA1
—
—
C2IN1-
—
Y
—
4
19
21
21 ANA2 DAC1OUT1 C1IN0+
—
—
—
—
IOCA2
—
—
VREF- (DAC5) C2IN0+
VREF- (ADC)
—
Y
—
5
20
22
22 ANA3 VREF+ (DAC5) C1IN1+
—
—
—
—
IOCA3
—
MDCIN1⁽¹⁾
—
VREF+ (ADC)
Y
—
6
21
23
23 ANA4
—
—
T0CKI⁽¹⁾
—
—
—
IOCA4
—
MDCIN2⁽¹⁾
—
Y
—
7
22
24
24 ANA5
—
—
—
—
—
—
IOCA5
—
MDMIN⁽¹⁾
SS1⁽¹⁾
Y
—
14
29
33
31 _ANA6
—
—
—
—
—
—
IOCA6
—
—
—
Y
CLKOUT
OSC2
13
28
32
30 ANA7
33
8
9
8
ANB0
34
9
10
9
ANB1
35
10
11
10 ANB2
—
—
—
—
C2IN1+
—
—
C1IN3-
—
C2IN3-
—
—
—
—
—
—
IOCA7
—
—
CWG1⁽¹⁾ ZCDIN IOCB0
—
INT0⁽¹⁾
—
—
—
IOCB1
INT1⁽¹⁾
—
—
—
—
IOCB2
—
INT2⁽¹⁾
—
—
Y
OSC1
CLKIN
—
SS2⁽¹⁾
Y
—
—
SCK2⁽¹⁾
Y
SCL2^(3,4)
—
—
SDI2⁽¹⁾
Y
—
SDA2^(3,4)
36
11
12
11 ANB3
—
C1IN2-
—
—
—
—
IOCB3
—
—
C2IN2-
37
12
14
14 ANB4
—
—
T5G⁽¹⁾
—
—
—
IOCB4
—
—
38
13
15
15 ANB5
—
—
T1G⁽¹⁾
—
—
—
IOCB5
—
—
—
Y
—
—
Y
—
—
Y
—
39
14
16
16 ANB6
—
—
—
—
—
40
15
17
17 _ANB7 DAC1OUT2
—
T6AIN⁽¹⁾
—
—
15
30
34
32 ANC0
—
—
T1CKI⁽¹⁾
—
—
T3CKI⁽¹⁾
T3G⁽¹⁾
16
31
35
35 ANC1
—
—
—
CCP2⁽¹⁾
—
—
IOCB6
CK2⁽¹⁾
—
—
IOCB7 _RX2/DT2⁽¹⁾
—
—
IOCC0
—
—
—
IOCC1
—
—
—
Y
ICSPCLK
—
Y
ICSPDAT
—
Y
SOSCO
—
Y
SOSCIN
SOSCI
1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers (Register 17-1).
2: All pin outputs default to PORT latch data. Any pin can be selected as a peripheral digital output with the PPS output selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
4: These pins are configured for I2C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be
standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds.