PIC18LF24K Datasheet, PDF (7/594 Pages) –

Pin Allocation Tables
TABLE 1: 28-PIN ALLOCATION TABLE (PIC18(L)F26K40)
I/O⁽²⁾
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
Note 1:
2:
3:
4:
2
27
ANA0
—
C1IN0-
—
—
—
—
IOCA0
—
—
C2IN0-
—
Y
—
3
28
ANA1
—
C1IN1-
—
—
—
—
IOCA1
—
—
C2IN1-
—
Y
—
4
1
ANA2
DAC1OUT1
C1IN0+
—
—
—
—
IOCA2
—
—
VREF- (DAC)
C2IN0+
VREF- (ADC)
—
Y
—
5
2
ANA3
VREF+ (DAC)
C1IN1+
—
—
—
—
IOCA3
—
MDCIN1⁽¹⁾
—
Y
—
VREF+ (ADC)
6
3
ANA4
—
—
T0CKI⁽¹⁾
—
—
—
IOCA4
—
MDCIN2⁽¹⁾
—
Y
—
7
4
ANA5
—
—
—
—
—
—
IOCA5
—
MDMIN⁽¹⁾
SS1⁽¹⁾
Y
—
10
7
ANA6
—
—
—
—
—
—
IOCA6
—
—
—
Y
CLKOUT
OSC2
9
6
ANA7
21
18
ANB0
22
19
ANB1
23
20
ANB2
—
—
—
—
—
—
IOCA7
—
—
C2IN1+
—
—
CWG1⁽¹⁾ ZCDIN IOCB0
—
INT0⁽¹⁾
—
C1IN3-
—
C2IN3-
—
—
—
IOCB1
INT1⁽¹⁾
—
—
—
—
—
—
—
IOCB2
—
INT2⁽¹⁾
—
—
Y
OSC1
CLKIN
—
SS2⁽¹⁾
Y
—
—
SCK2⁽¹⁾
Y
SCL2^(3,4)
—
—
SDI2⁽¹⁾
Y
—
SDA2^(3,4)
24
21
ANB3
—
C1IN2-
—
—
—
—
IOCB3
—
—
C2IN2-
25
22
ANB4
—
—
T5G⁽¹⁾
—
—
—
IOCB4
—
—
26
23
ANB5
—
—
T1G⁽¹⁾
—
—
—
IOCB5
—
—
—
Y
—
—
Y
—
—
Y
—
27
24
ANB6
—
—
—
—
—
—
IOCB6
CK2⁽¹⁾
—
28
25
ANB7
DAC1OUT2
—
T6AIN⁽¹⁾
—
—
—
IOCB7 RX2/DT2⁽¹⁾
—
—
Y
ICSPCLK
—
Y
ICSPDAT
Default peripheral input. Input can be moved to any other pin with the PPS input selection registers (Register 17-1).
All pin outputs default to PORT latch data. Any pin can be selected as a peripheral digital output with the PPS output selection registers.
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
These pins are configured for
standard TTL/ST as selected
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to any of these pins. PPS
input buffer thresholds.
assignments
to
the
other
pins
(e.g.,
RB1)
will
operate,
but
input
logic
levels
will
be