PIC18LF24K Datasheet, PDF (144/594 Pages) –

PIC18(L)F26/45/46K40
11.4 Register Definitions: Nonvolatile Memory
REGISTER 11-1: NVMCON1: NONVOLATILE MEMORY CONTROL 1 REGISTER
R/W-0/0
R/W-0/0
NVMREG<1:0>
U-0
R/S/HC-0/0 R/W/HS-x/q R/W-0/0 R/S/HC-0/0
—
FREE
WRERR
WREN
WR
bit 7
R/S/HC-0/0
RD
bit 0
Legend:
R = Readable bit
x = Bit is unknown
‘0’ = Bit is cleared
W = Writable bit
-n = Value at POR
‘1’ = Bit is set
HC = Bit is cleared by hardware
S = Bit can be set by software, but not cleared
U = Unimplemented bit, read as ‘0’
bit 7-6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
NVMREG<1:0>: NVM Region Selection bit
10 =Access PFM Locations
x1 = Access User IDs, Configuration Bits, Rev ID and Device ID
00 = Access Data EEPROM Memory Locations
Unimplemented: Read as ‘0’
FREE: Program Flash Memory Erase Enable bit⁽¹⁾
1 = Performs an erase operation on the next WR command
0 = The next WR command performs a write operation
WRERR: Write-Reset Error Flag bit^(2,3,4)
1 = A write operation was interrupted by a Reset (hardware set),
or WR was written to 1’b1 when an invalid address is accessed (Table 10-1, Table 11-1)
or WR was written to 1’b1 when NVMREG<1:0> and address do not point to the same region
or WR was written to 1’b1 when a write-protected address is accessed (Table 10-2).
0 = All write operations have completed normally
WREN: Program/Erase Enable bit
1 = Allows program/erase and refresh cycles
0 = Inhibits programming/erasing and user refresh of NVM
WR: Write Control bit^(5,6,7)
When NVMREG points to a Data EEPROM Memory location:
1 = Initiates an erase/program cycle at the corresponding Data EEPROM Memory location
When NVMREG points to a PFM location:
1 = Initiates the PFM write operation with data from the holding registers
0 = NVM program/erase operation is complete and inactive
RD: Read Control bit⁽⁸⁾
1 = Initiates a read at address pointed by NVMREG and NVMADR, and loads data into NVMDAT
0 = NVM read operation is complete and inactive
Note 1:
2:
3:
4:
5:
6:
7:
8:
This can only be used with PFM.
This bit is set when WR = 1 and clears when the internal programming timer expires or the write is
completed successfully.
Bit must be cleared by the user; hardware will not clear this bit.
Bit may be written to ‘1’ by the user in order to implement test sequences.
This bit can only be set by following the unlock sequence of Section 11.1.4 “NVM Unlock Sequence”.
Operations are self-timed and the WR bit is cleared by hardware when complete.
Once a write operation is initiated, setting this bit to zero will have no effect.
The bit can only be set in software. The bit is cleared by hardware when the operation is complete.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 144