PIC18LF24K Datasheet, PDF (540/594 Pages) –

PIC18(L)F26/45/46K40
TABLE 37-3: POWER-DOWN CURRENT (IPD)^(1,2)
PIC18LF26/45/46K40
Standard Operating Conditions (unless otherwise stated)
PIC18F26/45/46K40
Standard Operating Conditions (unless otherwise stated)
VREGPM = 1
Param.
No.
Symbol
Device Characteristics
Min.
Typ.†
Max.
+85°C
Max.
+125°C
Units
VDD
Conditions
Note
D200 IPD
IPD Base
— 0.05
2
9
A 3.0V
D200 IPD
D200A
IPD Base
—
0.4
4
—
20
—
12
A 3.0V
—
A 3.0V VREGPM = 0
D201
IPD_WDT
Low-Frequency Internal Oscillator/
WDT
—
0.4
3
10
A 3.0V
D201
IPD_WDT
Low-Frequency Internal Oscillator/
WDT
—
0.6
5
13
A 3.0V
D202 IPD_SOSC Secondary Oscillator (SOSC)
—
0.6
5
13
A 3.0V
D202 IPD_SOSC Secondary Oscillator (SOSC)
—
0.8
8.5
15
A 3.0V
D203 IPD_FVR FVR
—
31
—
—
A 3.0V FVRCON = 0X81 or 0x84
D203 IPD_FVR FVR
—
32
—
—
A 3.0V FVRCON = 0X81 or 0x84
D204 IPD_BOR Brown-out Reset (BOR)
—
9
14
18
A 3.0V
D204 IPD_BOR Brown-out Reset (BOR)
—
14
19
21
A 3.0V
D205 IPD_LPBOR Low-Power Brown-out Reset (LPBOR) —
0.5
—
—
A 3.0V
D205 IPD_LPBOR Low-Power Brown-out Reset (LPBOR) —
0.7
—
—
A 3.0V
D206 IPD_HLVD High/Low Voltage Detect (HLVD)
—
31
—
—
A 3.0V
D206
D207
D207
IPD_HLVD
IPD_ADCA
IPD_ADCA
High/Low Voltage Detect (HLVD)
ADC - Active
ADC - Active
—
32
—
— 250
—
— 280
—
—
A 3.0V
—
A 3.0V ADC is converting ⁽⁴⁾
—
A 3.0V ADC is converting ⁽⁴⁾
D208 IPD_CMP Comparator
—
25
38
40
A 3.0V
D208 IPD_CMP Comparator
—
28
50
60
A 3.0V
† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: The peripheral current is the sum of the base IDD and the additional current consumed when this peripheral is enabled. The
peripheral ∆ current can be determined by subtracting the base IDD or IPD current from this limit. Max. values should be used
when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part
in Sleep mode with all I/O pins in high-impedance state and tied to VSS.
3: All peripheral currents listed are on a per-peripheral basis if more than one instance of a peripheral is available.
4: ADC clock source is FRC.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 540