PIC18LF24K Datasheet, PDF (404/594 Pages) –

PIC18(L)F26/45/46K40
27.4.1 AUTO-BAUD DETECT
The EUSART module supports automatic detection
and calibration of the baud rate.
In the Auto-Baud Detect (ABD) mode, the clock to the
BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG.
The Baud Rate Generator is used to time the period of
a received 55h (ASCII “U”) which is the Sync character
for the LIN bus. The unique feature of this character is
that it has five rising edges including the Stop bit edge.
Setting the ABDEN bit of the BAUDxCON register
starts the auto-baud calibration sequence. While the
ABD sequence takes place, the EUSART state
machine is held in Idle. On the first rising edge of the
receive line, after the Start bit, the SPxBRG begins
counting up using the BRG counter clock as shown in
Figure 27-6. The fifth rising edge will occur on the RXx
pin at the end of the eighth bit period. At that time, an
accumulated value totaling the proper BRG period is
left in the SPxBRGH, SPxBRGL register pair, the
ABDEN bit is automatically cleared and the RCxIF
interrupt flag is set. The value in the RCxREG needs to
be read to clear the RCxIF interrupt. RCxREG content
should be discarded. When calibrating for modes that
do not use the SPxBRGH register the user can verify
that the SPxBRGL register did not overflow by
checking for 00h in the SPxBRGH register.
The BRG auto-baud clock is determined by the BRG16
and BRGH bits as shown in Table 27-6. During ABD,
both the SPxBRGH and SPxBRGL registers are used
as a 16-bit counter, independent of the BRG16 bit set-
ting. While calibrating the baud rate period, the SPx-
BRGH and SPxBRGL registers are clocked at 1/8th the
BRG base clock rate. The resulting byte measurement
is the average bit time when clocked at full speed.
Note 1: If the WUE bit is set with the ABDEN bit,
auto-baud detection will occur on the byte
following the Break character (see Sec-
tion 27.4.3 “Auto-Wake-up on Break”).
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible.
3: During the auto-baud process, the
auto-baud counter starts counting at one.
Upon completion of the auto-baud
sequence, to achieve maximum accuracy,
subtract 1 from the SPxBRGH:SPxBRGL
register pair.
TABLE 27-6: BRG COUNTER CLOCK RATES
BRG16 BRGH
BRG Base
Clock
BRG ABD
Clock
1
1
FOSC/4
FOSC/32
1
0
FOSC/16
FOSC/128
0
1
FOSC/16
FOSC/128
0
Note:
0
FOSC/64
FOSC/512
During the ABD sequence, SPxBRGL and
SPxBRGH registers are both used as a
16-bit counter, independent of the BRG16
setting.
FIGURE 27-6:
AUTOMATIC BAUD RATE CALIBRATION
BRG Value
RXx pin
XXXXh
0000h
Start
Edge #1
bit 0 ^{bit 1}
Edge #2
bit 2 ^{bit 3}
Edge #3
bit 4 ^{bit 5}
Edge #4
bit 6 ^{bit 7}
001Ch
Edge #5
Stop bit
BRG Clock
Set by User
ABDEN bit
RCIDL
RCxIF bit
(Interrupt)
Read
RCxREG
SPxBRGL
XXh
SPxBRGH
XXh
Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
Auto Cleared
1Ch
00h
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 404