PIC18LF24K Datasheet, PDF (443/594 Pages) –

PIC18(L)F26/45/46K40
31.5.8 CONTINUOUS SAMPLING MODE
Setting the ADCONT bit in the ADCON0 register
automatically retriggers a new conversion cycle after
updating the ADACC register. That means the ADGO
bit is set to generate automatic retriggering, until the
device Reset occurs or the A/D Stop-on-interrupt bit
(ADSOI in the ADCON3 register) is set (correct logic).
31.6 Register Definitions: ADC Control
31.5.9 DOUBLE SAMPLE CONVERSION
Double sampling is enabled by setting the ADDSEN bit
of the ADCON1 register. When this bit is set, two
conversions are required before the module will
calculate threshold error (each conversion must still be
triggered separately). The first conversion will set the
ADMATH bit of the ADSTAT register and update
ADACC, but will not calculate ADERR or trigger ADTIF.
When the second conversion completes, the first value
is transferred to ADPREV (depending on the setting of
ADPSIS) and the value of the second conversion is
placed into ADRES. Only upon the completion of the
second conversion is ADERR calculated and ADTIF
triggered (depending on the value of ADCALC).
REGISTER 31-1: ADCON0: ADC CONTROL REGISTER 0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
U-0
ADON
ADCONT
—
ADCS
—
bit 7
R/W-0/0
ADFM
U-0
R/W/HC-0
—
ADGO
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HC = Bit is cleared by hardware
bit 7
ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled
bit 6
ADCONT: ADC Continuous Operation Enable bit
1 = ADGO is retriggered upon completion of each conversion trigger until ADTIF is set (if ADSOI is
set) or until ADGO is cleared (regardless of the value of ADSOI)
0 = ADC is cleared upon completion of each conversion trigger
bit 5
Unimplemented: Read as ‘0’
bit 4
ADCS: ADC Clock Selection bit
1 = Clock supplied from FRC dedicated oscillator
0 = Clock supplied by FOSC, divided according to ADCLK register
bit 3
Unimplemented: Read as ‘0’
bit 2
ADFM: ADC results Format/alignment Selection
1 = ADRES and ADPREV data are right-justified
0 = ADRES and ADPREV data are left-justified, zero-filled
bit 1
Unimplemented: Read as ‘0’
bit 0
ADGO: ADC Conversion Status bit
1 = ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle. The bit is
cleared by hardware as determined by the ADCONT bit
0 = ADC conversion completed/not in progress
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 443