PIC18LF24K Datasheet, PDF (374/594 Pages) –

PIC18(L)F26/45/46K40
After the write to the SSPxBUF, each bit of the address
will be shifted out on the falling edge of SCL until all
seven address bits and the R/W bit are completed. On
the falling edge of the eighth clock, the master will
release the SDA pin, allowing the slave to respond with
an Acknowledge. On the falling edge of the ninth clock,
the master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT Status bit of the SSPxCON2
register. Following the falling edge of the ninth clock
transmission of the address, the SSPxIF is set, the BF
flag is cleared and the Baud Rate Generator is turned
off until another write to the SSPxBUF takes place,
holding SCL low and allowing SDA to float.
26.10.6.1 BF Status Flag
In Transmit mode, the BF bit of the SSPxSTAT register
is set when the CPU writes to SSPxBUF and is cleared
when all eight bits are shifted out.
26.10.6.2 WCOL Status Flag
If the user writes the SSPxBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL bit is set and the contents of the
buffer are unchanged (the write does not occur).
The WCOL bit must be cleared by software before the
next transmission.
26.10.6.3 ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit of the SSPxCON2
register is cleared when the slave has sent an Acknowl-
edge (ACK = 0) and is set when the slave does not
Acknowledge (ACK = 1). A slave sends an Acknowl-
edge when it has recognized its address (including a
general call), or when the slave has properly received
its data.
26.10.6.4 Typical transmit sequence:
1. The user generates a Start condition by setting
the SEN bit of the SSPxCON2 register.
2. SSPxIF is set by hardware on completion of the
Start.
3. SSPxIF is cleared by software.
4. The MSSP module will wait the required start
time before any other operation takes place.
5. The user loads the SSPxBUF with the slave
address to transmit.
6. Address is shifted out the SDA pin until all eight
bits are transmitted. Transmission begins as
soon as SSPxBUF is written to.
7. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit of the SSPxCON2 register.
8. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the
SSPxIF bit.
9. The user loads the SSPxBUF with eight bits of
data.
10. Data is shifted out the SDA pin until all eight bits
are transmitted.
11. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit of the SSPxCON2 register.
12. Steps 8-11 are repeated for all transmitted data
bytes.
13. The user generates a Stop or Restart condition
by setting the PEN or RSEN bits of the
SSPxCON2 register. Interrupt is generated once
the Stop/Restart condition is complete.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 374