PIC18LF24K Datasheet, PDF (161/594 Pages) –

PIC18(L)F26/45/46K40
13.6 CRC Check Value
The CRC check value will be located in the CRCACC
registers after the CRC calculation has finished. The
check value will depend on two mode settings of the
CRCCON register: ACCM and SHIFTM.
When the ACCM bit is set, the CRC module augments
the data with a number of zeros equal to the length of
the polynomial to align the final check value. When the
ACCM bit is not set, the CRC will stop at the end of the
data. A number of zeros equal to the length of the
polynomial can then be entered into CRCDAT to find
the same check value as augmented mode.
Alternatively, the expected check value can be entered
at this point to make the final result equal 0.
When the CRC check value is computed with the
SHIFTM bit set, selecting LSb first, and the ACCM bit
is set then the final value in the CRCACC registers will
be reversed such that the LSb will be in the MSb
position and vice versa. This is the expected check
value in bit reversed form. If you are creating a check
value to be appended to a data stream then a bit
reversal must be performed on the final value to
achieve the correct checksum. You can use the CRC to
do this reversal by the following method:
• Save CRCACC value in user RAM space
• Clear the CRCACC registers
• Clear the CRCXOR registers
• Write the saved CRCACC value to the CRCDAT
input
The properly oriented check value will be in the
CRCACC registers as the result.
13.7 CRC Interrupt
The CRC will generate an interrupt when the BUSY bit
transitions from 1 to 0. The CRCIF Interrupt Flag bit of
the PIR7 register is set every time the BUSY bit
transitions, regardless of whether or not the CRC
interrupt is enabled. The CRCIF bit can only be cleared
in software. The CRC interrupt enable is the CRCIE bit
of the PIE7 register.
13.8 Configuring the CRC
The following steps illustrate how to properly configure
the CRC.
1. Determine if the automatic program memory
scan will be used with the scanner or manual
calculation through the SFR interface and
perform the actions specified in Section
13.5 “CRC Data Sources”, depending on which
decision was made.
2. If desired, seed a starting CRC value into the
CRCACCH/L registers.
3. Program the CRCXORH/L registers with the
desired generator polynomial.
4. Program the DLEN<3:0> bits of the CRCCON1
register with the length of the data word - 1 (refer
to Example 13-1). This determines how many
times the shifter will shift into the accumulator for
each data word.
5. Program the PLEN<3:0> bits of the CRCCON1
register with the length of the polynomial -2
(refer to Example 13-1).
6. Determine whether shifting in trailing zeros is
desired and set the ACCM bit of the CRCCON0
register appropriately.
7. Likewise, determine whether the MSb or LSb
should be shifted first and write the SHIFTM bit
of the CRCCON0 register appropriately.
8. Write the CRCGO bit of the CRCCON0 register
to begin the shifting process.
9a. If manual SFR entry is used, monitor the FULL bit
of the CRCCON0 register. When FULL = 0,
another word of data can be written to the
CRCDATH/L registers, keeping in mind that
CRCDATH should be written first if the data has
more than eight bits, as the shifter will begin upon
the CRCDATL register being written.
9b. If the scanner is used, the scanner will
automatically stuff words into the CRCDATH/L
registers as needed, as long as the SCANGO bit
is set.
10a.If using the Flash memory scanner, monitor the
SCANIF (or the SCANGO bit) for the scanner to
finish pushing information into the CRCDATA
registers. After the scanner is completed,
monitor the CRCIF (or the BUSY bit) to
determine that the CRC has been completed
and the check value can be read from the
CRCACC registers. If both the interrupt flags are
set (or both BUSY and SCANGO bits are
cleared), the completed CRC calculation can be
read from the CRCACCH/L registers.
10b.If manual entry is used, monitor the CRCIF (or
BUSY bit) to determine when the CRCACC
registers will hold the check value.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 161